LDj3SNuD 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) ... * Update AILEmitterCtx.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs		2018-10-25 19:10:41 -03:00
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ACryptoHelper.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInst.cs
AInstEmitAlu.cs	Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)	2018-10-13 23:35:16 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs
AInstEmitFlow.cs	Remove cold methods from the CPU cache (#224)	2018-09-19 17:07:56 -03:00
AInstEmitHash.cs
AInstEmitMemory.cs
AInstEmitMemoryEx.cs	Thread scheduler rewrite (#393)	2018-09-18 20:36:43 -03:00
AInstEmitMemoryHelper.cs	More flexible memory manager (#307)	2018-08-15 15:59:51 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs	Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)	2018-10-25 19:10:41 -03:00
AInstEmitSimdCmp.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
AInstEmitSimdCrypto.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInstEmitSimdCvt.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
AInstEmitSimdHash.cs	Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)	2018-08-16 21:44:44 -03:00
AInstEmitSimdHelper.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
AInstEmitSimdLogical.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs	Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)	2018-10-13 23:35:16 -03:00
AInstEmitSimdShift.cs	Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)	2018-10-25 19:10:41 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs
ASoftFallback.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
ASoftFloat.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
AVectorHelper.cs	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00