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ryujinx-mirror2/ARMeilleure/IntermediateRepresentation
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gdkchan f0824fde9f
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 
* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
2022-01-21 12:47:34 -03:00
..
BasicBlock.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
BasicBlockFrequency.cs Implement block placement (#1549) 2020-09-19 20:00:24 -03:00
Comparison.cs Improve branch operations (#1442) 2020-08-05 08:52:33 +10:00
IIntrusiveListNode.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
Instruction.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
Intrinsic.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
IntrusiveList.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
MemoryOperand.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
Multiplier.cs
Operand.cs Optimize HybridAllocator (#2637) 2021-09-29 01:38:37 +02:00
OperandKind.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
OperandType.cs
Operation.cs Optimize HybridAllocator (#2637) 2021-09-29 01:38:37 +02:00
PhiOperation.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
Register.cs
RegisterType.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00