LDj3SNuD 894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) ... * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs		2018-10-13 23:35:16 -03:00
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ABlock.cs	Added support for more shader instructions and texture formats, fix swapped channels in RGB565 and RGBA5551? texture formats, allow zero values on blending registers, initial work to build CFG on the shader decoder, update the BRA instruction to work with it (WIP)	2018-05-29 20:37:10 -03:00
ACond.cs
ADataOp.cs
ADecoder.cs	Remove cold methods from the CPU cache (#224)	2018-09-19 17:07:56 -03:00
ADecoderHelper.cs
AIntType.cs
AOpCode.cs	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
AOpCodeAdr.cs
AOpCodeAlu.cs
AOpCodeAluImm.cs
AOpCodeAluRs.cs
AOpCodeAluRx.cs
AOpCodeBfm.cs
AOpCodeBImm.cs
AOpCodeBImmAl.cs
AOpCodeBImmCmp.cs	[CPU] Fix CBZ/CBNZ with 32 bits operands	2018-04-06 17:22:26 -03:00
AOpCodeBImmCond.cs
AOpCodeBImmTest.cs
AOpCodeBReg.cs
AOpCodeCcmp.cs
AOpCodeCcmpImm.cs
AOpCodeCcmpReg.cs
AOpCodeCsel.cs
AOpCodeException.cs
AOpCodeMem.cs
AOpCodeMemEx.cs
AOpCodeMemImm.cs
AOpCodeMemLit.cs
AOpCodeMemPair.cs
AOpCodeMemReg.cs
AOpCodeMov.cs
AOpCodeMul.cs
AOpCodeSimd.cs	Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) instructions, fix for NvFlinger sometimes missing free buffers	2018-02-24 11:19:28 -03:00
AOpCodeSimdCvt.cs
AOpCodeSimdExt.cs	Add SMLAL (vector), fix EXT instruction	2018-03-06 21:36:49 -03:00
AOpCodeSimdFcond.cs
AOpCodeSimdFmov.cs
AOpCodeSimdImm.cs	CPU fix for the cases using a Mask with shift = 0	2018-03-14 01:59:22 -03:00
AOpCodeSimdIns.cs
AOpCodeSimdMemImm.cs
AOpCodeSimdMemLit.cs
AOpCodeSimdMemMs.cs	Enable all ld/st (single structure) instructions	2018-03-30 18:06:02 -03:00
AOpCodeSimdMemPair.cs
AOpCodeSimdMemReg.cs
AOpCodeSimdMemSs.cs	Enable all ld/st (single structure) instructions	2018-03-30 18:06:02 -03:00
AOpCodeSimdReg.cs	Add MUL (vector by element), fix FCVTN, make svcs use MakeError too	2018-03-05 16:18:37 -03:00
AOpCodeSimdRegElem.cs	Add MLA (vector by element), fixes some cases of MUL (vector by element)?	2018-03-15 22:36:47 -03:00
AOpCodeSimdRegElemF.cs	Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)	2018-10-13 23:35:16 -03:00
AOpCodeSimdShImm.cs	Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)	2018-09-08 14:24:29 -03:00
AOpCodeSimdTbl.cs
AOpCodeSystem.cs
AShiftType.cs
IAOpCode.cs
IAOpCodeAlu.cs
IAOpCodeAluImm.cs
IAOpCodeAluRs.cs
IAOpCodeAluRx.cs
IAOpCodeCond.cs
IAOpCodeLit.cs
IAOpCodeSimd.cs