GreemDev-Ryujinx/ChocolArm64
LDj3SNuD be31f5b46d Improve CountLeadingZeros() algorithm, nits. (#219)
* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update ASoftFallback.cs

* Update ASoftFallback.cs

* Update AInstEmitSimdArithmetic.cs
2018-07-14 15:07:44 -03:00
..
Decoder
Decoder32
Events Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
Exceptions
Instruction Improve CountLeadingZeros() algorithm, nits. (#219) 2018-07-14 15:07:44 -03:00
Instruction32
Memory Query multiple pages at once with GetWriteWatch (#222) 2018-07-08 16:55:15 -03:00
State Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
Translation Remove broken adds/cmn with condition check optimization (#218) 2018-07-03 21:54:05 -03:00
ABitUtils.cs
AOpCodeTable.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AOptimizations.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00
AThread.cs Fix some thread sync issues (#172) 2018-06-21 23:05:42 -03:00
ATranslatedSub.cs
ATranslatedSubType.cs
ATranslator.cs
ChocolArm64.csproj Add linux-x64 to RID property to make tests works on linux (#205) 2018-06-30 12:43:04 -03:00